Dynamic memory (DRAM) is a type of random access memory used in computing devices, primarily on a PC. DRAM stores each data bit in a separate passive electronic component, which is located inside the integrated circuit board. Each electrical component has two value states in one bit, called 0 and 1. It must be updated frequently, otherwise the information disappears. DRAM has one capacitor and one transistor per bit, unlike static random access memory (SRAM), which requires 6 transistors. The capacitors and transistors used are extremely small. There are millions of capacitors and transistors that fit on a single memory chip.
The development of dynamic technology
Being one of the forms of memory technology, the dynamic memory of RAM arose from the development of the first microprocessors and related developments of integrated circuits. In the mid-1960s, integrated circuits began to appear in some modern electronic products, which previously used the form of magnetic memory in the form of one small ferrite toroid for each element. Naturally, this “core” memory was very expensive, and the integrated versions were more attractive in the long run.
The idea of DRAM technology appeared relatively early on the timeline of semiconductor integrated circuits. The early form was used in the Toshiba calculator, which was released in 1966 from a discrete component, and then two years later the idea was patented. The next stage in technology development occurred in 1969, when Honeywell, which entered the computer market, asked Intel to manufacture dynamic memory using three transistor cell ideas. The resulting DRAM was named Intel 1102 and appeared in early 1970. However, the device had several problems, after which Intel developed a new technology that worked more reliably.
The resulting new device appeared at the end of 1970 and was called Intel 1103. The technology advanced even further when in 1973 MOSTEK released its MK4096. As the part number shows, the device had a capacity of 4 k. Its main advantage was that it included a multiplexed approach to rows and columns. This new approach made it possible to fit into packages with fewer contacts. As a result, the cost advantage has grown over previous approaches with each increase in memory size.
This allowed MOSTEK technology to gain more than 75% of the global market share. In the end, MOSTEK lost to the Japanese manufacturers because they were able to produce better devices at a lower price.
Varieties of memory and their purpose
DRAM is dynamic memory, and SRAM is static memory. The DRAM chips on the board are updated every few milliseconds. This is done by overwriting the data in the module. The chips that need updating are volatile memory. DRAM directly accesses memory, remembers memory for a short period, and loses its data when the power is turned off.
SRAM is a volatile memory that is static and does not need to be updated. Since it runs much faster, it is used in registers and cache memory. SRAM stores data and operates at higher speeds than dynamic memory with a motherboard, because it is much cheaper to manufacture.
DRAM is one of the semiconductor memory options that a system designer can use when creating a computer. Alternate memory options include static RAM (SRAM), electrically erasable read-only programmable memory (EEPROM), NOR Flash, and NAND Flash. Many systems use more than one type of memory.
Types of printed circuit boards and reading systems
The three main types of printed circuit boards that contain memory chips are two built-in memory modules (DIMMs), single-line memory modules (SIMMs), and Rambus memory modules in the line (RIMMs).
Today, most motherboards use DIMMs. The module update frequency for DRAM is every few milliseconds (1/1000 seconds). This update is performed by a memory controller located on the chipset of the motherboard. Since the update logic is used for automatic updates, the DRAM card is quite complex.
There are various systems used for updating, but all methods require that the counter keep track of the line, which should be updated as follows. DRAM cells are organized as a square set of capacitors, typically 1024 by 1024 cells. When the cell is in the read state, an entire line is read and the update is written back. When in the “write” state, the whole line is “read”, one value is changed, and then the entire line is overwritten.
Depending on the system, there are DRAM chips that contain a counter while other systems rely on peripheral device update logic. Access times are around 60 nanoseconds, while SRAM can reach 10 nanoseconds. In addition, the DRAM cycle time is much longer than that of SRAM. The cycle time is shorter because it does not need to stop between calls and updates.
DRAM vs SRAM
DRAM is the successor to SRAM. Memory designers reduced the number of elements per bit and excluded differential bit lines to preserve the chip area for creating DRAM. As a result, it is cheaper to produce than SRAM. But SRAM retains some advantages over DRAM. Comparison of static and dynamic memory:
- SRAM does not need to be updated, since it works on the principle of switching the current stream in one of two directions instead of holding the charge in the storage place.
- It is usually used for cache memory, which can be accessed faster than DRAM.
- SRAM is capable of reading and writing byte bits and reads and writes faster than DRAM, which writes data at the byte level and reads at the multibyte page level.
- The differences in power are determined depending on whether the system is in active or sleep mode. DRAM requires less power than SRAM in the active state, but SRAM consumes significantly less power in standby mode.
There are many types or interfaces for communicating with DRAM. These include Fast Page Mode (FPM DRAM), Advanced Data from DRAM (EDO RAM) and Synchronous DRAM (SDRAM). SDRAM is the generic name for DRAM types synchronized to the microprocessor clock speed. These include Single Bit Rate SDRAM (SDR), Dual Bit Rate SDRAM (DDR), DDR2 SDRAM, DDR3 SDRAM and DDR4 SDRAM.
RAM working principle
Dynamic memory devices have MOS technology, which underlies the design, manufacture and operation. After seeing how DRAM works, you can see that in the base RAM or DRAM, a capacitor is used to store each bit of data and a transmitting device is a MOSFET, which acts as a switch.
The charge level on the capacitor of the memory cell determines whether this particular bit is logical “1” or “0” - the presence of charge in the capacitor indicates logic “1”, and the absence of charge indicates logical “0”. Dynamic memory allocation RAM has a certain format, as a result of which it can be densely packed on a silicon chip, and this makes it very cheap. Two lines are connected to each dynamic RAM cell - the Word line (W / L) and the bit line (B / L), so that the desired cell inside the matrix can read or write data.
Base cell
The shown base memory cell would be one of many thousands or millions of such cells in a full memory chip. They can have a capacity of 256 Mbps or more. To improve write and read capabilities and speed, perform dynamic memory allocation with division into submatrices. Having multiple subarrays reduces words and bit strings, and this reduces access time to individual cells. For example, dynamic RAM 256 Mbit, DRAM can be divided into 16 smaller 16 Mbit arrays.
Linear controls the input of the transmission lines, while bit bins are connected to the FET channel and are eventually connected to sensitivity amplifiers. There are two ways to organize bit strings:
- Stacked bit lines. You can consider a pair of adjacent discharge lines as one discharge line, folded in half, with a connection on a slot connected to a shared amplifier. This format provides additional noise immunity, but at the expense of compactness.
- Open bit lines. In this configuration, lines are placed between two submatrices, thereby connecting each signal amplifier with one bit line in each array. This offers a more compact solution than coiled bit lines due to noise immunity.
Dynamic RAM update operation
One of the problems associated with this circuit is that capacitors do not hold their charge indefinitely because there is some leakage on the capacitor. It would be unacceptable for the memory to lose its data, and to overcome this problem, the data is periodically updated. Data is read and written, and this ensures that any leakage is overcome and the data is restored.
One of the key elements of DRAM is the fact that data is periodically updated. Typically, manufacturers indicate that each row should be updated every 64 ms. This time interval complies with JEDEC standards for dynamic RAM update periods.
There are many ways you can upgrade. Some processor systems update each line together every 64 ms. Other systems update one line at a time, but this has the disadvantage that with large memories, the update frequency becomes very fast. Other systems, especially real-time systems in which speed matters, take an approach where part of the semiconductor memory is simultaneously dependent on an external timer that controls the rest of the system. Thus, this does not interfere with the operation of the system.
Regardless of which method is used, it is necessary that the counter can track the next line in DRAM that needs to be updated. Some chips include a counter, otherwise an additional device must be added for this purpose. It might seem that the update schemes needed for DRAM will complicate the overall memory scheme and make it more expensive. However, it was found that an additional circuit is not a serious problem if it can be integrated into a memory chip. And it was also found that this memory is much cheaper and has a much larger capacity than that of the other main rival - static RAM (SRAM).
Signal to noise ratio
As memories grow in size, the signal-to-noise ratio problem becomes very important because it can cause data corruption problems. It depends on the ratio of the capacitance of the storage capacitor in the DRAM to the capacity of the Word line or the bit to which the charge is reset when the cell is accessed. As the density of bits on the microcircuit increases, the ratio deteriorates as the area of the cell decreases, because more cells are added to the bit line.
For this reason, it is important to store both high voltage on the capacitive capacitor and increase the capacity of the DRAM for given areas as much as possible. This is very important because the sensitivity of a small charge on the capacitor of the memory cell is one of the most difficult areas of the memory chip design - DRAM. As a result of this, some complex circuits were included in the memory chips.
DRAM chips are widely used, and the technology has proven itself very well. And memory chips and plugins are available to expand the memory of computers and many other devices. Although DRAM has its drawbacks, it is still widely used because it offers many advantages in terms of cost size and satisfactory speed, it is not the fastest, but still much faster than some other types of memory.
Asynchronous technology
There are several types in the DRAM family, including asynchronous, synchronous, EDO, BEDO, FPM, and others. Besides the type of memory technology, it can also be contained in several types of IC packets. DRAM is also available in module formats and there are several types of memory modules, including DIMMs, SIMMs, RIMMs, etc. Therefore, you need to be aware of all the different types of DRAMs and the formats in which memory can be received, installed, and used.
When studying the technology of memory itself, there is a wide variety of different types of DRAM. Asynchronous DRAM, is the main type on which all other types are based. Asynchronous have connections for power, address inputs, and bidirectional data lines. Although this type of DRAM is asynchronous, the system is started by a memory controller that is synchronized, and this limits the speed of the system to multiply the clock speed. However, DRAM itself is not synchronous.
Memory allocation
Dynamic memory allocation is the process by which computer programs and services are assigned a physical or virtual memory space. In fact, this is the process of backing up a partial or full part of computer memory to run programs and processes. Memory allocation is achieved through a process known as memory management through the operating system and software applications.
Dynamic memory allocation has two main types:
- The allocation of static memory, the program is allocated memory at compile time.
- Dynamic memory allocation, programs are allocated with memory at runtime.
The memory allocation process is very similar to managing physical and virtual memory. Programs and services are assigned a specific memory in accordance with their requirements during execution. As soon as the program completes its work, or is idle, the memory is freed and assigned to another program or combined in the primary memory.
Memory usage optimization
The arduino dynamic memory is made in the form of flash. Where the program itself is stored and cannot be changed, except when the user downloads a new program called a “sketch” from the computer and saves what he downloaded, even if the power is turned off. When the sketch is checked or downloaded, the PC will inform you in the window how much flash is and how much is used if the “detailed mode” in the settings is enabled.
Each time a new sketch is loaded, it overwrites the old one. Arduino has only one program at a time, and when the Arduino is powered up, the program starts forever. Most modern Arduinos have about 32 thousand flash memory, which is quite small and limits the size of the programs (thumbnails) that you can download. But SRAM is the real limit for many things. The user really needs to be careful in planning in order to minimize what really needs to be saved. And if you try to use too much - Arduino just won't work. The user cannot even perform the most minimal debugging actions until the PC is rebooted.
SRAM is the most valuable memory item on the Arduino. Although the disadvantages of SRAM are probably the most common memory problems on the Arduino. They are difficult to diagnose. If the program fails inexplicably, there is a good chance that the user has broken the stack due to a lack of SRAM. There are a number of things you can do to reduce the use of SRAM:
- Delete unused variables.
- Reserve rows.
- Move persistent data to PROGMEM.
- Decrease buffer size.
- Reduction of oversized variables.
Any variable that the user defines either at the top of the program, inside the function, or even on the fly in something like a for loop, is likely to use SRAM, although some variables are never stored in SRAM. Each time Arduino is started by turning it on or reset, all its variables are reinitialized by default, and it needs to re-examine the environment with which it works.
Working with dynamic memory is an important important aspect that should be considered when developing a system. In fact, there is a third type of memory - EEPROM, which can be written, and it will be saved in case of power failure. Arduino can write 300 EEPROM per second, if the user is careless, then theoretically this speed can destroy a memory cell in 5 minutes, and the entire EEPROM in two days.