🙏🏿 🐿️ 🆕 RISC processor architecture 🈲 🧢 ☺️

RISC architecture is a computer with a reduced set of instructions. It is a type of microprocessor architecture that uses a small optimized set of instructions, unlike the previous types of architectures with an extended set of algorithmic data. The term RISC was coined by David Patterson from the Berkeley RISC project.

Definition

A computer with a limited set of instructions is a device whose instruction set architecture (ISA) has an attribute set that allows it to have lower instruction cycles (CPI) than a complex command installed on a computer (CISC). General concept RISC is a computer concept that contains a small set of simple and general algorithms, but not an extended set of complex and specialized sequences. Another common feature of RISC is the load / storage architecture, where memory is accessed only using specific instructions.

History and Development

The first RISC projects came from IBM, Stanford and UC-Berkeley in the 70s and 80s. Twentieth century. The IBM 801, Stanford MIPS, and Berkeley RISC I and II were developed with a similar philosophy that came to be known as RISC. Some design features were characteristic of most RISC processors:

Execution time of one cycle: processors have CPI - time to execute instructions of one cycle. This is due to the optimization of each command on the CPU.
Pipeline processing: a technical algorithm that allows the simultaneous execution of parts or steps of instructions for more efficient processing of instructions.
Large register list: RISC's design philosophy usually includes a larger number of registers to prevent excessive memory interactions.

Although a number of computers from the 1960s and 70s were previous RISC models, the modern concept dates back to the 1980s. In particular, two projects at Stanford and the University of California scale this conceptual idea. Stanford MIPS will become a commercially successful model, while the University of Berkeley has given the name to the whole concept, commercialized as SPARC. Another success of this era was the efforts of IBM, which ultimately led to Power Architecture. As these trends developed in the late 1980s, and especially in the early 1990s, many similar projects flourished, representing the main force in the Unix workstation market, as well as embedded processors in laser printers, routers, and similar products. .

Pros and Cons of RISC Architecture

The easiest way to explore the benefits and vulnerabilities of the RISC architecture is to correlate it with the previous CISC architecture. The main goal of the CISC architecture is to complete the task in fewer assembly lines. This is achieved by creating processor equipment that can understand and perform a number of operations. For this specific task, the CISC processor comes with a specific instruction (MULT). When executed, this command loads two values into separate registers, multiplies the operands in the executive module, and then stores the product in the corresponding register. Thus, the entire task of multiplying two numbers can be completed with one instruction: MULT 2: 3, 5: 2. CISC and RISC architecture - the previous and subsequent architectural solution.

MULT is what is known as a “complex instruction”. The command works directly in the computer's memory banks and does not require the programmer to explicitly call any load or save functions. She is very similar to a team in a higher level language. For example, if we assume that a represents a 2: 3 value and b represents a 5: 2 value, then this command is identical to the expression C a = a * b.

One of the main advantages of this system is that the compiler has to do a minimum of work in order to translate the formulation of a high-level language into an assembly. Since the code is relatively short, very little RAM is required to store instructions. In a comparative analysis of the CISC and RISC architecture of the processors, the emphasis is on the implementation of complex instructions directly in the hardware.

RISC Approach

RISC processors use only elementary instructions that execute in a single clock cycle. Thus, the MULT instruction described above can be divided into three separate instructions: LOAD, which transfers data from the memory bank to the PROD register, which finds the product of two operands located inside the registers, and STORE, which transfers data from the register to the memory banks. To complete the exact series of steps described in the CISC approach, the programmer will need to encode four assembly lines:

LOAD A, 2: 3.
LOAD B, 5: 2.
PROD A, B.
STORE 2: 3, A.

Initially, this might seem like a much less efficient way to complete the operation, since there are more lines of code and more RAM is needed to store assembly-level instructions. The compiler also needs to do more work to convert the high-level language language into code of this form.

Comparison of CISC and RISC

The following are comparatives of CISC and RISC architecture:

CISC:

Emphasis on hardware.
Includes many hours of complex instructions.
Small code sizes, high cycles per second.
Transistors used to store complex instructions.

RISC:

Focus on software.
A shortened instruction that does not require a lot of time.
Low cycles per second, large code sizes.
Spends more transistors on memory registers.

The RISC strategy brings some very important benefits. Since each command requires only one measure, the entire program will execute in approximately the same amount of time as the multi-cylinder MULT command. These RISC “shorthand instructions” require less hardware transistors than complex instructions, leaving more room for shared registers. Since all instructions are executed in a single time (for example, one clock cycle), pipelining is possible.

Process characteristic

Separating LOAD and STORE instructions actually reduces the amount of work a computer needs to do. After executing a CISC-style MULT command, the processor automatically erases the registers. If one of the operands must be used for another calculation, the processor must reload the data from the memory bank into the register. In RISC, the operand will remain in the register until another value is loaded on it.

The CISC approach attempts to minimize the number of instructions for each program by sacrificing the number of cycles per instruction. RISC, on the contrary, reduces the number of cycles due to the instructions for each program.

Difficulties in commercial implementation

Despite the benefits of RISC-based processing, decades passed before RISK chips were commercially viable. This was largely due to the lack of software support.

Although Apple's Power Macintosh line, which used RISC and Windows NT chips, is compatible with RISC, Windows 3.1 and Windows 95 were designed with CISC in mind. Many companies were reluctant to risk the emerging RISC technology. Without commercial interest, processor developers could not manufacture RISC chips in volumes large enough to make their price competitive.

Another major obstacle was the presence of Intel. Despite the fact that their CISC chips have become increasingly cumbersome and complex to develop, Intel has the resources to develop powerful processors. Although RISC chips could outperform Intel's efforts in certain areas, the differences were not large enough to convince customers to change technology.

The general advantage of RISC

Today, Intel x86 is the only chip that preserves the CISC architecture. This is primarily due to advancement in other areas of computer technology. The price of RAM has fallen sharply. In 1977, 1 MB of DRAM cost about $ 5,000. By 1994, the same amount of memory costs only $ 6 (including inflation). Compiler technology has also become more sophisticated, so the use of RISC RAM and the emphasis on software have become ideal.

Instruction set philosophy

An erroneous understanding of the definition of RISK is the idea that the procedures are eliminated, which leads to a reduced set of algorithms. Over the years, RISC procedures have been increasing, and nowadays many of them have a wider range of functions than the CISC CPUs.

The term “reduced set of procedures” means a description of the fact that the amount of work performed by each instruction is reduced (no more than one memory cycle) compared with the complicated CISC procedures, which require dozens of cycles to execute one command. The RISC architecture usually has separate I / O and data manipulation algorithms.

Instruction format

Most RISC architectures have fixed-length instructions (typically 32 bits) and simple coding, which greatly simplifies the selection, decoding, and output of logic. One of the drawbacks of 32-bit instructions is the reduction in code density, which is an unfavorable factor for embedded computing on workstations and servers. RISC architectures were originally designed for maintenance. To solve this problem, several architectures, such as ARM, Power ISA, MIPS, RISC-V and Adipteva Epiphany, have an optional short abbreviated instruction format or command compression function. SH5 also follows this pattern, although it has evolved in the opposite direction by adding longer multimedia instructions to the original 16-bit encoding.

Use of equipment

For any given level of overall performance, the RISC chip typically has far fewer transistors designed for the core logic, which initially allowed designers to increase register size and internal parallelism.

Other features commonly found in RISC architectures:

The average processor performance approaches one instruction per cycle.
Uniform format of instructions - one word is used with the operation code in the same positions for easier decoding.
All general purpose registers can be used as a source / destination in all instructions, simplifying the development of the compiler (floating point registers are often stored separately).
Simple modes with complex addressing, executed by sequences of commands.
Several types of data in hardware (for example, byte string or BCD).

RISC designs also present Harvard's memory model, where commands and data are conceptually separated. This means that changing the memory in which the code is stored may not affect the instructions executed by the processor (since the CPU has a separate cache of instructions and data) until a special synchronization instruction is issued. On the other hand, this allows you to access caches at the same time, which often improves performance.

Features of RISC Architecture

At the initial stage of the development of the computer industry, programming was conducted in assembly language or machine code, which encouraged the use of powerful and easy-to-use instructions. Therefore, the developers of the CPU tried to design algorithms that can perform as much work as possible. With the advent of higher-level languages, architects began to create special instructions for the direct implementation of certain central mechanisms. The second overall goal was to provide all possible addressing modes for each algorithm, known as orthogonality, to facilitate the implementation of the compiler.

The attitude towards that time was that the hardware design was more mature than the compiler design, therefore, in itself, it is also the reason for the introduction of parts of the functionality in the hardware or microcode, and not only in the memory-limited compiler (or in its generated code). After the advent of RISC, this approach became known as complex instruction set computing, or CISC.

Processors also had relatively few registers for several reasons:

A large number of registers implies longer storage and restoration of contents on the machine stack and requires a large number of instruction bits as qualifiers, which means less dense code.
CPU registers are more expensive than external memory cells.
Limited PCBs or integrated circuits.

Practical use

RISC architecture of the processor is now used on a wide range of platforms: from smartphones and tablet PCs to some of the most high-performance supercomputers, such as computer K (the leader in the list of the top 500 in 2011).

By the beginning of the 21st century, most low-profile and mobile systems were based on the RISC architecture. Examples:

ARM architecture dominates the market for low-power and low-cost embedded systems (200-1800 MHz in 2014). It is used in most Android systems, Apple iPhone and iPad, Microsoft Windows Phone (formerly Windows Mobile), RIM devices (topic.risc.architecture), Nintendo Game Boy Advance, DS / 3DS and Switch.
The MIPS line (used at one time on many SGI computers), and now on the PlayStation, PlayStation 2, Nintendo 64 (ipb.risc.architecture), PlayStation Portable game consoles, and residential gateways such as Linksys WRT54G.
Hitachi SuperH, used in the Sega Super 32X, Saturn and Dreamcast (viewtopic.php.risc.architecture), is now developed and marketed by Renesas as SH4.
Atmel AVR is used in a variety of product lines: from portable Xbox controllers to BMW cars.
RISC-V (vbulletin.risc.architecture), the fifth Berkeley RISC ISA open source, with 32-bit address space, a small kernel of an integer instruction set, experimental "compressed" ISA for code density and intended for standard and special extensions.
Workstations, servers and supercomputers.
MIPS (powered.by.smf.risc.architecture), Silicon Graphics (in 2006 it stopped creating systems based on MIPS).
SPARC, Oracle (formerly Sun Microsystems) and Fujitsu (phorum.risc.architecture).
The IBM Power Architecture used by most IBM supercomputers, mid-range servers, and terminal stations.
PA-RISC Hewlett-Packard (phpbb.risc.architecture), also referred to as HP-PA (discontinued at the end of 2008).
Alpha, used in single-board computers, workstations, servers, and supercomputers from Digital Equipment Corporation, Compaq, and HP (discontinued since 2007).
RISC-V (powered.by.phpbb.risc.architecture), the fifth Berkeley RISC ISA, open source, with 64 or 128-bit address spaces and a whole kernel extended with floating point, atomization and vector processing, and designed for extensions with instructions for networks, input-output, data processing. The 64-bit superscalar Rocket design is available for download.

Comparison with other architectures

Some processors were specifically designed with a very small set of instructions, but these designs are significantly different from traditional RISC architectures, so they were provided with other data, such as a minimal instruction set (MISC) or transport initiated architecture (TTA).

RISC architectures have traditionally had little success in the desktop and commodity server markets, where x86-based platforms remain the dominant processor architecture. However, this may change as ARM-based processors are designed for higher performance systems. Manufacturers, including Cavium, AMD and Qualcomm, have released server processors based on the ARM architecture. ARM also partnered with Cray in 2017 to create a supercomputer based on the ARM architecture. Microsoft's leading computer industry company announced that it plans to support the PC version of Windows 10 on devices based on Qualcomm Snapdragon in 2017 as part of a partnership with Qualcomm. These devices will support x86-based Win32 software using an x86 processor emulator.

However, in addition to the desktop arena, the ARM RISC architecture is widely used in smartphones, tablets, and many forms of embedded devices. Also, Intel Pentium Pro (P6) uses an internal RISC processor core for its processors.

While the initial development of the RISC processor architecture was significantly different from the CISC innovation projects, by 2000 the highest-performance processors in the RISC line almost did not differ from the highest-performance processors in the CISC line.

RISC processor architecture